(a) Field of the Invention:
The present invention relates to a semiconductor device and a process for manufacturing same, and more particularly it pertains to a modified integrated injection logic (IIL) device or a modified merged transistor logic (MTL) device including lateral bipolar transistors and vertical field effect transistors (including static induction transistor), and also concerns an improved process for manufacturing same.
(b) Description of the Prior Art:
A modified integrated injection logic (IIL) device employing a bipolar transistor of lateral structure as its injector or load transistor and a field effect transistor of vertical type including static induction transistor (SIT) as its driver or inverter transistor has been proposed. In general, this type of IIL device (hereinafter to be referred to as SITL device which is an abbreviation of a Static Induction Transistor Logic device) is superior, in such aspects as operating speed, power dissipation, simplicity of manufacturing process and so forth, to conventional IIL devices employing bipolar transistors as its driver and injector transistors, and this SITL has such a basic structure as shown in FIG. 1.
In FIG. 1, a known IIL device includes a semiconductor wafer 10 consisting of a heavily doped n.sup.+ type semiconductor substrate 12 of a row resistivity and a lightly doped n.sup.- type semiconductor layer 14 of a high resistivity. In the layer 14 are formed a heavily doped p.sup.+ type semiconductor layer 16 of a low resistivity, a pair of heavily doped p.sup.+ type semiconductor layers 18 and 18' of a low resistivity, and a heavily-doped n.sup.+ type semiconductor layer 24 of a low resistivity. The respective layers 14, 16 and 18 jointly constitute a bipolar transistor of lateral structure to serve as an injector transistor of the device. More particularly, the p.sup.+ type layer 16 serves as the emitter of the injector transistor; the p.sup.+ type layer 18 to serve as the collector; and a portion 20 of the n.sup.- type layer 14 which is sandwiched between the p.sup.+ type layers 16 and 18 to serve as the base of the injector transistor. On the other hand, an improved field effect transistor of vertical type (also referred to SIT which is an abbreviation of a Static Induction Transistor) to function as a driver or inverter transistor of the device is formed by the n.sup.+ type layer 12 to serve as the source, the n.sup.+ type layer 24 to serve as the drain, the p.sup.+ type layers 18 and 18' to serve as the gates, and that n.sup.- type portion 22 of the n.sup.- type layer 14 which is sandwiched between the respective gates 18 and 18', to serve as the current rent channel. As described, the collector of the injector bipolar transistor and the gates of the driver field effect transistor are merged in the single common layer 18, thus effectively performing carrier injection from the injector transistor into the driver transistor gates. The respective gates 18 and 18' are usually formed to be continuous or wired together to be held at a same potential.
In case no bias voltage is externally applied to the gates 18 and 18', the current channel 22 of the driver transistor is almost entirely depleted by only the diffusion potential of the gates and accordingly held substantially non-conductive. That is, the driver transistor is an SIT of the normally-off type, i.e. of an enhancement mode. Therefore, in order to render the current channel conductive, it is necessary to forwardly bias the gates slightly and thereby to inject carriers from the gates into the current channel through the gate-channel p-n junctions formed along the boundaries between the gates and the current channel. With the structure illustrated in FIG. 1, however, a larger number of carriers which are actually useless for the channel-conduction control are injected from the gates into the high-resistivity region of the layer 14 other than that really serving as the current channel 22, and this, in turn, contributes to degradation of carrier injection efficiency and also brings about a carrier storage effect which should slow down the switching speed of the driver transistor. This problem also holds true to the injector bipolar transistor.
Recently, an SITL device which has been improved further than that mentioned above has been proposed in U.S. Patent Application No. 854494 filed on Nov. 23, 1977 by Terumoto NONAKA, one of the present inventors. In this improved SITL device, the gate region of the driver SIT is formed to directly contact at least one of the source and drain regions and/or the emitter region of the injector bipolar transistor is formed to establish a direct contact with the source region, in order to eliminate as much as possible the useless high-resistivity region which would be responsible for the aforementioned undesirable injection of carriers and carrier storage effect.